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PIC18F2455/2550/4455/4550

DS39632E-page 170

2009 Microchip Technology Inc.

17.2.2.8

Internal Regulator

The PIC18FX455/X550 devices have a built-in 3.3V reg-

ulator to provide power to the internal transceiver and

provide a source for the internal/external pull-ups. An

external 220 nF (±20%) capacitor is required for stability.

The regulator can be enabled or disabled through the

VREGEN Configuration bit. When enabled, the voltage

is visible on pin VUSB whenever the USBEN bit is also

set. When the regulator is disabled (VREGEN = 0), a

3.3V source must be provided through the VUSB pin for

the internal transceiver.

17.2.3

USB STATUS REGISTER (USTAT)

The USB Status register reports the transaction status

within the SIE. When the SIE issues a USB transfer

complete interrupt, USTAT should be read to determine

the status of the transfer. USTAT contains the transfer

endpoint number, direction and Ping-Pong Buffer

Pointer value (if used).

The USTAT register is actually a read window into a

four-byte status FIFO, maintained by the SIE. It allows

the microcontroller to process one transfer while the

SIE processes additional endpoints (Figure 17-4).

When the SIE completes using a buffer for reading or

writing data, it updates the USTAT register. If another

USB transfer is performed before a transaction

complete interrupt is serviced, the SIE will store the

status of the next transfer into the status FIFO.

Clearing the transfer complete flag bit, TRNIF, causes

the SIE to advance the FIFO. If the next data in the

FIFO holding register is valid, the SIE will reassert the

interrupt within 5 TCY of clearing TRNIF. If no additional

data is present, TRNIF will remain clear; USTAT data

will no longer be reliable.

FIGURE 17-4:

USTAT FIFO

Note:

The drive from VUSB is sufficient to only

drive an external pull-up in addition to the

internal transceiver.

Note 1: Do not enable the internal regulator if an

external regulator is connected to VUSB.

2: VDD must be equal to or greater than

VUSB at all times, even with the regulator

disabled.

Note:

The data in the USB Status register is valid

only when the TRNIF interrupt flag is

asserted.

Note:

If an endpoint request is received while the

USTAT FIFO is full, the SIE will

automatically issue a NAK back to the

host.

Data Bus

USTAT from SIE

4-byte FIFO

for USTAT

Clearing TRNIF

Advances FIFO

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